The present invention relates to an EPROM (erasable programmable read-only memory) having memory cells formed of semiconductor devices such as MOSFET (insulated gate field effect transistor) or FAMOS (floating gate avalanche injection MOSFET), and particularly its word line drive circuits.
An example of EPROM is shown in Japanese Patent Application Laid-open No. 246098/1985, which will next be described with reference to FIG. 1.
In FIG. 1, part of a memory cell array in a conventional EPROM is shown. For the purpose of simplicity, the memory cell array is shown to comprises 2.times.2 memory cells.
The memory cells 1-1 to 1-4 are formed of semiconductor devices such as FAMOS. The control gates of the memory cells 1-1 and 1-2 which are aligned in the horizontal directions are connected together to a word line 2-1. Similarly, the control gates of the memory cells 1-3 and 1-4 which are aligned in the horizontal direction are connected together to a word line 2-2. The drains of the memory cells 1-1 and 1-3 which are aligned in the vertical direction are connected together to a bit line 3-1. Similarly, the drains of the memory cells 1-2 and 1-4 which are aligned in the vertical direction are connected together to a bit line 3-2.
The sources of the memory cells 1-1 to 1-4 are connected to the ground (=0 V).
First, the writing operation that is, writing in the memory cells 1-1 to 1-4 will be explained.
Assume that the memory cell 1-1 is to be selected. A relatively high voltage (e.g., 12.5 V) is applied to the selected word line 2-1, while 0 V is applied to the unselected word line 2-2. Moreover, a relatively high voltage (e.g., 9 V) is applied to the selected bit line 3-1 while the unselected bit line 3-2 is brought to the open state. In the selected memory cell 1-1, because of the high control gate voltage, a large amount of channel current is created. The channel current is accelerated by the high electric field between the drain and the source, and generates hot electrons with a high energy. The hot electrons are injected into the floating gate, exceeding the energy barrier of the gate oxide film. Injection of the hot electrons into the floating gate means that "information has been written". The threshold of the memory cell 1-1 in which the information has been written will become higher (e.g.,7 V) than the voltage (e.g., 5 V) of the selected word line 2-1 during reading. The threshold of the memory cells 1-2 to 1-4 in which information has not been written is low (e.g., 2 V). Thus, whether the threshold is high or low indicate the information "0" or "1 is stored.
The operation during reading will now be described.
When for instance the memory cell 1-1 is selected, 5 V is applied to the selected word line 2-1 and 0 V is applied to the unselected word line 2-2. A relatively low voltage is applied to the selected bit line 3-1 in order to prevent generation of hot electrons due to a high electric field between the drain and source, which can cause an erroneous writing operation. The unselected bit line 3-2 is made in an open state. If the selected memory cell 1-1 is an unwritten memory cell (in which "1" is stored), the threshold is 2 V and since 5 V is being applied to the control gate, the memory cell 1-1 becomes on and a current flows through the drain and source. This current is detected by a sense amplifier not, shown, and amplified, and output to an output terminal of the EPROM as a high level (H-level) signal. If the selected memory cell is a written memory cell (in which "0" is stored), the threshold is 7 V, and since 5 V is being applied to the control electrode the memory cell 1-1 is off and no current flows through the drain and source. This fact that no current flows is detected by the sense amplifier and amplified and output to the output terminal of the EPROM as a low level (L-level) signal.
If the threshold of the memory cell that has not been written ("1" is stored) is denoted by Vthm and if the voltage of the selected word line is denoted by Vwl, the drain current of the unwritten memory cell is proportional to (Vwl-Vthm) when the memory cell is operating in the triode region, and is proportional to (Vwl-Vthm).sup.2 when the memory cell is operating in the pentode region. As was described earlier, the sense amplifier detects the current flowing through the memory cell. In order to quickly read the unwritten memory cell the sense amplifier must operate quickly, and for this the current flowing through the memory cell must be increased. Accordingly, a word line drive circuit for quickly driving the control gate of the memory cell, i.e., the selected word line to the voltage of the power supply is required.
FIG. 2 shows a word line drive circuit of the conventional EPROM described in the above-mentioned publication. FIG. 3 shows a predecoder circuit incorporated in the word line drive circuit. The word line drive circuit shown in FIG. 2 comprises a decoder circuit 10 for decoding the internal address signals a1 to a3 and selecting the word lines 2-1 to 2-8, and voltage booster circuit 20 connected to the output node N3 of the decoder circuit 10, and pairs of N-channel MOS (NMOS) transistors 30-1 to 30-8 and 31-1 to 31-8.
The decoder circuit 10 comprises depletion-type NMOS transistors 11, 16, enhancement-type NMOS transistors 12 to 14, 17 to 19, and intrinsic-type NMOS transistor 15 whose threshold is 0 V. The internal address signals a-1 to a-3 supplied to the gates of the NMOS transistors 12 to 14 are in phase with the external address signals supplied to an address buffer, not shown. The address buffer also generates internal address signals opposite in phase. Vcc denotes the power supply voltage, ovs/PD/ denotes a signal input to the gate of the NMOS transistor 15 and is at the high level during operation and at the low level during stand-by to reduce power consumption. N1 denotes a node connected to the gate of the NMOS transistor 17 and N2 denotes a node connected to the gate of the NMOS transistor 19.
The booster circuit 20 gradually boosts the voltage of the node N3 when the node N3 is raised to the high level responsive to the input of the internal address signals a-1 to a-3. The booster circuit 20 comprises a depletion-type NMOS transistor 21, intrinsic-type NMOS transistors 22 and 23, a capacitor 24 and a terminal receiving an oscillating signal OC. Pairs of NMOS transistors 30-1 to 30-8 and 31-1 to 31-8 are enhancement-type transistors. Connected to the junctions of the transistors, e.g., 30-1 and 31-1, of the respective pairs are word lines 2-1 to 2-8. Supplied to the gates of the NMOS transistors 30-1 to 30-8 and 31-1 to 31-8 are complementary predecode signals Pr1 to Pr8 and Pr1 to Pr8, which are generated by the predecode circuit in FIG. 3.
The predecode circuit shown in FIG. 3 comprises AND gates 40-1 to 40-8 and inverters 41-1 to 41-8. Supplied to the respective AND gates 40-1 to 40-8 are complementary internal address signals a4, a5, a6; a4, a5, a6; a4, a5, a6; a4, a5, a6; a4, a5, a6; a4, a5, a6; a4, a5, a6; a4, a5, a6. The AND gates 40-1 to 40-8 output the predecode signals Pr1 to Pr8, and inverted predecode signals Pr1 to Pr8 are output from the inverters 41-1 to 41-8. For instance, when the internal address signals a4, a5 and a6 are all at the high level, the predecode signal Pr1 at the output of the AND gate 40-1 is at the high level, while other predecode signals Pr2 to Pr8 are all at the low level.
Operation for driving the word line that is selected during reading will now be described with reference to FIG. 2.
Assume for instance that the word line 2-1 is to be selected. The internal address signals a1, a2 and a3 input to the respective gates of the NMOS transistors 12, 13 and 14 shown in FIG. 2 are all set at the low level, and the internal address signals a4, a5 and a6 input to the AND gates 40-1 to 40-8 are all set at the high level. Then, the NMOS transistors 12 to 14 are turned off and the node N1 is raised to the high level, and the node N2 thereby falls to the low level and the node N3 is raised to the high level. Because the internal address signals a4, a5 and a6 are all high, the predecode signal Pr1 at the output of the AND gate 40-1 is high, and the inverted predecode signal Pr1 is low. The other predecode signals Pr2 to Pr8 become low and the inverted predecode signals Pr2 to Pr8 become high. As a result, the NMOS transistor 30-1 is turned on and the NMOS transistor 31-1 is turned off, so that the word line 2-1 is driven to the high level, while the other word lines 2-2 to 2-8 are at the low level.
The above-described system has the following problem. Let us consider what will be the actual voltage during reading in a situation in which the power supply voltage Vcc is 5 V and the writing voltage is also 5 V in the circuit shown in FIG. 2.
Assume that the substrate potential is 0 V, the threshold of the enhancement-type NMOS transistor when there is no back-bias effect is set at 0.8 V and the threshold of the depletion-type NMOS transistor when there is no back-bias effect is set at -2.0 V, and the threshold of the intrinsic-type NMOS transistor when there is no back-bias effect is set at 0 V.
When the word line 2-1 is selected, the internal address signals a1, a2 and a3 which are at the low level are input and the NMOS transistors 12, 13 and 14 are turned off. The threshold of the depletion type NMOS transistor 11 is -1.8 V because of the back-bias effect due to the 5 V source voltage, so that the NMOS transistor 11 drives the node N1 to 5 V. The threshold of the enhancement-type NMOS transistor 18 is now 1 V because of the back-bias effect, so that it drives the node N3 to 4 V. The node N3 is thereafter gradually driven to 9 V by the booster circuit 20. When high-level internal address signals a4, a5, a6 are input to the AND gates 40-1 to 40-8 the predecode signal Pr1 is driven to the high level of 5 V. The inverted predecode signal Pr1 becomes the low level and the NMOS transistor 31-1 is turned off. Because the enhancement-type NMOS transistor 30-1 has the threshold 1 V with the back-bias effect, the word line 2-1 is driven only to 4 V which is the gate voltage 5 V of the NMOS transistor 30-1 minus the threshold 1 V. This means that during reading, the voltage applied to the gate of the NMOS transistor 30-1 is not sufficient and the potential of the word line 2-1 is lowered. As a result, the drain current through the selected unwritten memory cell is decreased and the reading speed is lowered.